As processor speeds continue to increase, different types of memory devices have been developed to keep up with increased processor speeds. The types of memory devices include static random access memories (SRAMs), dynamic random access memories (DRAMs), synchronous DRAMs (SDRAMs), Rambus® DRAMs (RDRAMs) (from Rambus, Inc.), and other types of memory devices.
In a memory subsystem using RDRAMs, the memory devices are connected to a Rambus channel that is capable of transferring data at up to 800 megahertz (MHz). In one arrangement, a Rambus channel is capable of supporting up to 32 RDRAMs. Basically, an RDRAM is a DRAM that incorporates Rambus interface circuitry. Typically, the Rambus channel is connected to a single memory controller that generates requests for data inside the RDRAMs. Multiple overlapped memory requests can be issued from the memory controller. The memory controller knows the time period required for an RDRAM to respond to a read or write request. For example, the memory controller can issue a read request to the memory device and expect the memory device to return the data in a given number of clock cycles. The memory controller schedules multiple read requests so only one memory device drives read data onto the data bus at any one time. By controlling the timing of the requests, the memory controller can have up to eight memory requests outstanding on the Rambus channel at any given time.
Conventional memory buses such as Rambus channels are usually configured to work with a single memory controller. Typically, the memory bus does not provide for tag data or other forms of identifiers to indicate the destination of data on the memory bus. The memory bus assumes there is only a single memory controller, so any data being returned from a memory device (such as in response to a read request) is targeted for the memory controller.
Although improvements in memory controller designs have enabled efficient memory controller operation, the limitation that only a single memory controller can reside on the memory bus poses various issues. For example, if multiprocessing is desired, a conventional arrangement has multiple processors residing on a host bus that is connected to a single memory controller, which translates requests from the processors to memory requests on a separate memory bus that is connected to memory devices. However, using two buses, a host bus and a memory bus, typically increases memory access delay.